1. Field of the Invention
The invention relates in general to integrated circuit (IC) testers and in particular to an IC tester having multiple pin channels.
2. Description of Related Art
A typical integrated circuit (IC) tester includes a set of channels, each connected to a separate pin of an IC device under test (DUT). The tester organizes a test into a succession of test cycles, and during any test cycle any channel may transmit a test signal to its corresponding DUT IO pin or may sample a DUT output signal to determine its state. When an IO pin is bi-directional, a channel may alternatively transmit a test signal to the DUT IO pin and sample a DUT output signal at that IO pin during another part of the test cycle. Some IC testers employ a centralized pattern generator that sends control data to each channel before the start of each test cycle for telling the channel what to do during the test cycle. For example, FIG. 1 depicts a prior art integrated circuit tester 10 for testing an IC DUT 12. Tester 10, suitably implemented on a single IC chip, includes a set of N channels {CH1, CH2 . . . CHN}, each for communicating with a separate IO pin (or terminal) of DUT 12. A clock signal generator 14 generates a master clock signal MCLK that signals the start of each test cycle. On each clock signal edge, a programmable pattern generator 16 supplies control data (FSET, TSET, and D1-DN) to channels CH1-CHN to tell them what to do during the next test cycle. All channels CH1-CHN receive the same FSET and TSET data values, but each channel CH1-CHN receives a separate corresponding one of data values D1-DN.
FSET Data
The FSET data supplied to each channel before the start of each test cycle references a pattern of test activities, if any, that the channel is to carry out during the test cycle. Each channel CH1-CHN can carry one or more of several kinds of test activities during a test cycle including turning on a test signal input to the DUT IO pin, driving the test signal to a high or low logic level, turning off (“tristating”) the test signal, or sampling a DUT output signal appearing at the DUT IO pin to determine whether it is of an expected state. Each channel CH1-CHN decodes the FSET data to learn the pattern of actions it is to carry out during the test cycle. Although all channels receive the same FSET data at the start of each test cycle, they do not necessarily decode the FSET data in the same way, and therefore they all do not necessarily perform the same pattern of test activities during the test cycle.
TSET Data
Each channel CH1-CHN generates a set of internal timing signals and uses edges of those timing signals to initiate the actions it carries out during a test cycle. Each channel decodes the TSET data supplied to the channel at the start of each test cycle to determine a time during the test cycle each timing signal edge is to occur. When the FSET data indicates that the channel is to carry out one or more test activities during a test cycle, it indicates a time during the test cycle at which each test activity is to occur by selecting a particular timing signal that is to initiate the test activity. Although all channels receive the same TSET data at the start of each test cycle, the manner in which each channel decodes the TSET data is also separately programmable for each channel, so that their timing signals need not necessarily have the same edge timing during any given test cycle.
D1-DN Data
Each channel CH1-CHN receives a corresponding one of input data values D1-DN from the pattern generator at the start of each test cycle, and each channel may use that data when carrying out the test activities specified by the FSET data. For example, the FSET data input to channel CH1 may tell the channel to drive a test signal input to a DUT IO pin to a state or sequence of states specified by the channel's D1 data input. The FSET data may tell channel CH1 to sample a DUT output signal appearing at the pin one or more times during a test cycle to determine whether it is of an expected state, the D1 data input to channel CH1 indicates the expected state of each DUT output signal sample.
Tester Programming
Before the start of a test, an external host computer 18, communicating with tester 10 via a computer bus (CBUS), programs pattern generator 16 to produce appropriate sequences of FSET, TSET and D1-DN data during the test and programs each channel CH1-CHN to appropriately decode its incoming FSET and TSET data. A random access memory (RAM) 20 supplies a separate one of a set of enable signals {E1, E2 . . . EN} to each channel CH1-CHN to tell the channel when it is to communicate with computer 18 via the CBUS. When computer 18 wants to write programming data only to a kth one (CHk) of channels CH1-CHN, it writes an address into register 22 causing enable RAM 20 to drive only the kth enable signal ENk true When computer 18 thereafter sends the programming data out via the CBUS, only the enabled channel CHk receives the programming data. When two or more of channels CH1-CHN are to decode the FSET and TSET data in the same way during a test, computer 18 can write an address into register 22 causing enable RAM 20 to concurrently enable all channels that are to receive the same programming data. Thereafter computer 18 can concurrently send the same programming data to all enabled channels.
Channel Architecture
FIG. 2 illustrates the internal architecture of channel CH1. Channels CH2-CHN are internally similar. A programmable decoder 24 decodes the TSET and FSET data arriving at the start of each test cycle to provide format control data FC to a DUT interface circuit 26 and timing control data TC to a timing signal generator 28 during the test cycle. Decoder 24 supplies the format control data FC to DUT interface circuit 26 to indicate a pattern of test activities the interface circuit is to carry out during the test cycle. Format control data FC may tell DUT interface circuit 26 to sample a DUT output signal appearing at the DUT IO pin to determine whether it is of an expected state as indicated by data D1 and/or to set a tristate test signal input to a single DUT IO pin to a particular state or to a state or succession of states indicated by data D1.
Timing signal generator 28 processes the MCLK signal to supply a set of timing reference signals TS1-TS4 to DUT interface circuit 26. The timing control data TC decoder 24 supplies to timing signal generator 28 at the start of each test cycle indicates a separate time during the test cycle at which an edge is to occur in each timing signal TS1-TS4. When the format control data FC tells DUT interface circuit 26 to carry out a test activity, it selects one of timing signals TS1-TS4 to initiate that test activity. DUT interface circuit 26 then initiates the test activity on the next occurrence of an edge of the selected timing signal. Since four separate timing signals TS1-TS4 are available to tell DUT interface circuit 26 when to carry out a test activity, DUT interface circuit 26 can carry out test activities at up to four different times during any test cycle.
When enabled by the EN1 signal, a bus interface circuit 29 permits computer 18 of FIG. 1 to program decoder 24 and DUT interface circuit via programming data sent via computer bus CBUS before the start of a test. At the end of a test, bus interface circuit 29 permits computer 18 to acquire test result data from DUT interface circuit 26 indicating whether any DUT output signal sample was of an unexpected state during any test cycle. Computer 18 also programs bus interface circuit 29 to provide control data to DUT interface circuit 26 for setting the high and low logic levels of the test signal and for setting the reference voltage levels DUT interface circuit 26 uses to determine whether the DUT output signal samples are of high or low logic levels.
FIG. 3 illustrates channel CH1 of FIG. 2 in more detail. A pair of RAMs 40 and 42 implement programmable decoder 24 of FIG. 2. DUT interface circuit 26 of FIG. 2 includes a tristate driver 30, a formatter circuit 32, a receiver 34 and a fail logic circuit 36. Timing signal generator 28 of FIG. 2 includes a master timing signal generator 46 and a set of timing verniers 38A-38D.
RAM 40 decodes the incoming FSET data to provide format control data FC to formatter 32 and fail logic circuit 36 at the start of each test cycle. The FC data tells formatter circuit 32 how to control the states of a set of control signals DH, DL and Z that tell driver 30 when to drive the test signal to a high or low logic level and when to tristate it. Receiver 34 monitors the DUT output signal and supplies a signal COMP to fail logic circuit 36 indicating whether it is of a high or low logic state. The format control data FC tells fail logic circuit 36 when, during any given test cycle, to sample the COMP signal input from receiver 34 and compare its state to its expected value as indicated by the D1 data input from pattern generator 16 of FIG. 1. Since fail logic circuit 36 can sample the COMP signal up to four times during any test cycle, the D1 data is suitably four bits wide to provide a separate bit for indicating the expected state of each of four COMP signal samples.
A master timing circuit 46 processes the MCLK signal to produce several timing reference signals TREF, each having the same frequency as the MCLK signal but being of a different phase, such that edges of the TREF signals are evenly distributed in time during each test cycle. RAM 42 decodes the TSET data to provide timing control data to a set of timing verniers 38A-38D that produce timing signals TS1-TS4 to tell each timing vernier 38A-38D when to produce an edge in its corresponding one of timing signals TS1-TS4 during the test cycle by interpolating between edges of selected TREF signals. The FC data input to formatter 32 tells the formatter when to change a state of the test signal input to the DUT by referencing one of timing signals TS1-TS4 that is to initiate the test signal state change action. The FC data input to fail logic circuit 36 tells the fail logic circuit when to sample the COMP signal by referencing one of timing signals TS1-TS4 that is to initiate the sampling operation.
Bus interface circuit 29 permits computer 18 of FIG. 1 to write or read access the various components of channel CH1 before or after the test when enable line EN1 is true. Computer 18 can write FSET decoding data into RAM 40 and TSET decoding data into RAMs 42A-42D to control the manner in which the channel decodes the FSET and TSET data. Computer 18 can write to registers in bus interface circuit 50 that supply control data to driver 30 and receiver 34 for controlling the logic levels of the test signal and the high and low logic detection levels of receiver 34. Computer 18 can also read access a memory within fail logic circuit 36 that the fail logic circuit uses to store data indicating each test cycle, if any, in which the sampled COMP signal state failed to match its expected state.
Thus each channel CH1-CHN of tester 10 of FIG. 1 can carry out up to four test activities per test cycle because each tester channel generate four timing signals TS1-TS4 that it can use to initiate each of up to four test activities. Tester 10 requires one channel CH1-CHN for each DUT IO pin, and can test any DUT having up to N pins It can also test more than one DUT concurrently if the total number of DUT IO pins is no larger than N. When tester 10 is implemented on a single IC chip, the number N of channels is limited by the size of the IC chip and the number of transistors and other components that can be formed on the IC. Therefore the number of DUT IO pins tester 10 can access is limited by the number N of channels that can be implemented on the IC chip.
Referring to FIG. 3, a substantial portion of the resources of each tester channel is devoted to decoding the FSET and TSET data to produce the format control data FC and timing signals TS1-TS4 needed to control test activities. Although, a channel needs four timing signals TS1-TS4 only when it must carry out four test activities during a single test cycle, in most IC tests, most tester channels need carry out no more than one or two test activities per test cycle. For example in many IC tests, a tester may change the state of a clock signal input to a DUT four times per test cycle but will change the states of all data signal inputs to the DUT no more than once or twice during any test cycle, and will sample each DUT output signal only once per test cycle. Thus a tester will not make full use of much of the decoding and timing signal generation resources of most of its tester channels during the test.
One approach to increasing the number of channels that can be implemented on an IC is reduce the size of each channel by providing channels that can carry out only one activity per test cycle. This reduces the size of the channels because it eliminates almost three quarters of the circuitry needed to decode the TSET data and produce timing signals, but in order to provide test signals with sufficient frequency, it is also necessary to reduce the test cycle period by a factor of four. This means that the speed of pattern generator 16 of FIG. 1 must be increased by a factor of four so that it can supply data at a four time higher rate than otherwise required when a channel can carry out four test activities per test cycle. Unfortunately, the necessary increase in speed of pattern generator 16 may not be attainable or may be attainable only at substantially increased cost.
What is needed is way to increase the total number DUT IO pins tester 10 can accommodate without substantially increasing the size of the IC needed to implement tester 10, or the frequency at which its pattern generator must operate.